1. Field of the Invention
The present invention relates to a semiconductor memory device that includes a self refresh function, and more specifically, to a self refresh control circuit and a self refresh test method of a semiconductor memory device.
2. Description of Related Art
In recent years, in semiconductor memory devices (or simply referred to as devices) such as synchronous DRAM (Synchronous Dynamic Random Access Memory; hereinafter referred to as SDRAM) or pseudo SRAM (Static Random Access Memory), low power consumption in a data holding period has been strongly demanded since a system that uses a battery such as a portable telephone has been spread.
In SDRAM, pseudo SRAM or the like, self refresh (hereinafter referred to as SR) operation that automatically performs refresh operation in a device is performed for the purpose of suppressing power consumption. In terms of power consumption, longer cycle of the SR timer is desirable. However, if the cycle of the SR timer becomes longer, data holding time of the memory cell becomes longer as well, which increases the risk of data holding fault of the memory cell.
In order to realize both of the low power consumption of the device and to improve reliability, a method has now become popular that makes the cycle of the SR timer longer at a low temperature or normal temperature where data holding time of the memory cell is long, and makes the cycle of the SR timer shorter at a high temperature where data holding time of the memory cell is short.
Further, the semiconductor memory device such as SDRAM, pseudo SRAM, eDRAM (Embedded DRAM), or memory, has become larger in capacity, and in some cases, a plurality of word lines are simultaneously activated in the SR operation. Thus, in some cases, the noise that occurs in the SR operation seriously obstructs the operation rather than the noise that occurs in the normal access operation.
From the background as above, a method of testing correlation between the SR timer characteristics and the data holding time of the memory cell while accelerating the noise that occurs in the SR operation in the production process has been required.
A semiconductor memory device disclosed in Dono will be described in detail with reference to FIGS. 12, 13, and 14. FIGS. 12, 13, and 14 are diagrams for describing the semiconductor memory device disclosed in Japanese Unexamined Patent Application Publication No. 2006-260630 (Dono). The semiconductor memory device disclosed in Dono is an SDRAM device that includes a mode register (not shown).
The SDRAM device conforms to JEDEC standard. When the SDRAM receives a mode register set command (MRS command), and an A7 pin (external pin) is in an “H” state and A0-A6 pins and A8-A13 pins have predetermined values, the SDRAM is designed to be put into a predetermined test mode.
In addition, the SDRAM is arranged to assert a test mode flag during the predetermined test mode. In this example, the asserted/negated test mode flag is used in refresh counter control. The mode register and the test mode are shown, for example, in Japanese Unexamined Patent Application Publication No. 2002-230996 (Sawada).
FIG. 12 is a block diagram showing a semiconductor memory device disclosed by Dono. As shown in FIG. 12, the semiconductor memory device includes a counter controller 10, a refresh counter 20, a row decoder 30, and a memory cell array 40. Some components are not shown in FIG. 12 for the sake of clarity.
The counter controller 10 includes a first input unit and a second input unit. The counter controller 10 generates a counter control signal 103 based on a refresh command signal 101 input to the first input unit and a test mode flag 102 input to the second input unit. The refresh command signal 101 instructs execution of refresh operation in a form of a pulse. In summary, pulses are generated in accordance with the number of times refresh operations are carried out on the refresh command signal 101.
More specifically, when the test mode flag 102 is negated, the counter controller 10 outputs the refresh command signal 101 as the counter control signal 103. When the test mode flag 102 is asserted, the counter controller 10 outputs a constant value as the counter control signal 103. In summary, the pulses are transmitted in accordance with the number of times refresh operations are carried out on the counter control signal 103 while the test mode flag 102 is negated. On the other hand, when the test mode flag 102 is asserted, the counter control signal 103 does not change even in the refresh operation.
The refresh counter 20 receives the counter control signal 103 and outputs a counter output 104. The refresh counter 20 includes a structure similar to that of a known semiconductor memory and counts the pulses included in the counter control signal 103 to generate the counter output 104. The counter output 104 is also called an internal address.
The row decoder 30 also includes a structure similar to that of a known semiconductor memory. The row decoder 30 decodes the counter output 104 to generate a plurality of row addresses 105, in accordance with which a plurality of word lines are activated. According to the above configuration, the refresh operation is performed on the memory cell that is connected to a plurality of word lines among the memory cells included in the memory cell array 40.
It is possible to know which internal address the counter output 104 generated by the refresh counter 20 indicates by employing various known techniques. One example includes using a reset function of a refresh counter when the refresh counter is provided with a reset function.
For example, by counting the number of refresh commands that are input after reset operation for the refresh counter 20, it is possible to know which value the refresh counter 20 outputs without directly monitoring the counter output 104. As it is already known how the row decoder 30 decodes the counter output 104, if an internal address can be specified, it is possible to know which is the word line that is actually activated, or which is the row address 105. Accordingly, it can be readily known whether the row address 105 includes a specific address to be directly tested.
In the semiconductor memory device disclosed by Dono as above, the counter controller 10 can cause the refresh counter 20 to stop the count operation at a time when the row address 105 includes a specific address that is a target of failure analysis. Accordingly, the refresh counter 20 keeps outputting a counter output (internal address) 104 that relates to a specific address. Thus, the refresh operation where a specific address is the refresh target can be repeated, and the failure analysis can be performed in a state of the refresh operation.
FIG. 13 shows a detailed structure of the counter controller 10 and the refresh counter 20 of the semiconductor memory device disclosed by Dono. FIG. 14 is a timing chart showing variation of signals of each part.
As shown in FIG. 13, the counter controller 10 includes an inverter 11 and a two input AND gate 12. The AND gate 12 is provided with one input unit to which a refresh command signal 101 is input and the other input unit to which a test mode flag 102 is input through the inverter 11.
From the structure shown in FIG. 13, it can be clearly understood that, while the test mode flag 102 is in an “L” state, the AND gate 12 outputs the counter control signal 103 corresponding to the refresh command signal 101. On the other hand, while the test mode flag 102 is in an “H” state, the AND gate 12 keeps outputting “L”.
The refresh counter 20 is provided with cascade connection of n (n is a natural number) sets of units, each of which including an input AND gate 21, a flip-flop (F/F) 22, and an output AND gate 23. Each of the flip-flops 22 is provided with a reset terminal (RST). The reset terminal is connected to a power up signal line 200. When a power is supplied to the semiconductor memory device, each of the flip-flops 22 is reset, and the counter output 104 takes default value “0”.
The address of the word line that should be selected by the row decoder 30 in the refresh operation can be obtained by decoding the internal address output from the refresh counter. As the digit number (bus width) of the internal address is fewer than that of the address input from the external terminal in the normal writing/reading operations, the number of word lines that is concurrently selected by the internal address in the refresh operation is larger than that in the normal operation.
Referring to FIG. 14, in the period from T0 to T2, the test mode flag 102 is negated, so that the pulses are appeared on the counter control signal 103 corresponding to the refresh command signal 101. As the refresh counter 20 counts the number of pulses appeared on the counter control signal 103, the counter output 104 is incremented every time the refresh command is issued.
However, at T3, the MRS command is issued, the A7 is placed in “H” and the A0-A6 and A8-A13 pins have the predetermined values so that the SDRAM is put into the predetermined test mode, and the test mode flag 102 is asserted.
In T4 and subsequent periods, there is no signal change on the counter control signal 103 even when the refresh command is issued, and the counter control signal 103 takes a constant value. In summary, the refresh command only reaches the counter controller 10, and is not transmitted to the refresh counter 20. Therefore, the refresh counter 20 stops the count operation and keeps outputting of the previous counter output 104. The test mode flag 102 in this example is the stop signal to cause the refresh counter 20 to stop the count operation.
In the example shown in FIG. 14, “0002”, which is the counter output 104 that is immediately before a predetermined test mode, is repeatedly output even in a certain test mode. In short, the refresh operation where the refresh target is a plurality of row addresses that correspond to “0002” is repeatedly performed by issuing the refresh commands.
As described above, according to Dono, the refresh operation that includes a specific address as a refresh target can be repeatedly performed, and the failure analysis can be performed with the state of the refresh operation.
FIG. 15 shows a flow chart of a refresh failure analysis disclosed by Dono that can be understood from the description above, which is a flow chart of a test method disclosed by Dono. First, in step S30, the refresh command is input, and the refresh counter is incremented to the interested address. Next, in step S31, the test mode is input, and the refresh counter is stopped to fix the internal address.
Then, in step S32, the refresh command is input so as to perform the refresh operation on only the interested address. Lastly, in step S33, the fault reproduction is judged. When varying the internal address, the test mode is cancelled and the state is made back to start to repeat the series of operation. Described above is a test method of the analysis in the refresh operation disclosed by Dono.
The example of Dono is the test method of the device that is operable by the refresh command signal 101 which is externally input. Thus, regarding the test including the operation of the internal self refresh timer (hereinafter referred to as SR timer), the test method of the data holding time of the memory cell using the refresh command control needs to be constructed after obtaining the temperature characteristics of the data holding time of the memory cell and the SR timer, validating each correlation, and setting a standard value of the SR timer in advance.
FIG. 10 shows temperature characteristics of data holding time of the memory cell and the SR timer in SR operation. As shown in FIG. 10, the device that tends to be the SR operation fault obstructs the expected operation as there is no operating margin when the temperature characteristics of the data holding time of the memory cell in SR operation in which a plurality of word lines are activated approaches the temperature characteristics of the SR timer.
The temperature characteristics varies in a production process due to production tolerance or the like. Thus, the correlation between the temperature characteristics of the data holding time of the memory cell and the temperature characteristics of the SR timer of the device varies, which brings difference with the standard value of the SR timer set in the alternative test verification.
According to this test, there is a problem that the originally intended test cannot be performed on the device that obstructs the SR operation due to the deterioration of correlation between temperature characteristics of the data holding time of the memory cell and the SR timer by the noise due to the active operation of the plurality of word lines.
Further, in International Patent Publication No. WO2004/027780 (Shinozaki), short refresh operation is performed in which the data holding fault of the memory cell is accelerated without sufficiently amplifying the voltage differences between the bit lines by reducing the active period. However, in this short refresh operation, the active time of the word lines or the bit lines is so short that the voltage differences between the bit lines is not sufficiently amplified. Accordingly, it is not possible to perform validation in which the active noise such as the interference of the adjacent word lines or bit lines is sufficiently given on the memory cell having process abnormality including VT abnormality. In short, sufficient validation cannot be performed on the possible data holding fault of the memory cell.